ADC (Successive Approximation Techinque)

Block diagram

Algorithm

The successive approximation Analog to digital converter circuit typically consists of four chief subcircuits:

1. A sample and hold circuit to acquire the input voltage (V_in).
2. An analog voltage comparator that compares V_in to the output of the internal DAC and outputs the result of the comparison to the successive approximation register (SAR).
3. A successive approximation register subcircuit designed to supply an approximate digital code of V_in to the internal DAC.
4. An internal reference DAC that supplies the comparator with an analog voltage equivalent of the digital code output of the SAR for comparison with V_in.

The successive approximation register is initialized so that the most significant bit (MSB) is equal to a digital 1. This code is fed into the DAC, which then supplies the analog equivalent of this digital code (V_ref/2) into the comparator circuit for comparison with the sampled input voltage. If this analog voltage exceeds V_in the comparator causes the SAR to reset this bit; otherwise, the bit is left a 1. Then the next bit is set to 1 and the same test is done, continuing this binary search until every bit in the SAR has been tested. The resulting code is the digital approximation of the sampled input voltage and is finally output by the DAC at the end of the conversion (EOC).

Souce: http://en.wikipedia.org/wiki/Successive_approximation_ADC

For a pratical ADC Chip..See the link
http://www.esnips.com/doc/ba12463b-13e8-4d01-abcc-4293761f9521/ADC_12b_ADCS7476
for its working see page no 17